1. Field of the Invention
The present invention relates to a method of manufacturing an isolation of integrated circuits. More particularly, the present invention relates to a method for manufacturing a shallow trench isolation.
2. Description of the Related Art
A complete integrated circuit is composed of a plurality of metal oxide semiconductor (MOS) transistors. Device isolation structures are used for isolating neighboring semiconductor devices so that any short circuiting between them is prevented. The conventional method of isolating semiconductor devices includes forming a field oxide (FOX) layer on a substrate by local oxidation of silicon (LOCOS). However, the field oxide layer that is formed has several problems. Considerable stresses are created at the junction between the field oxide layer and the substrate. Moreover, bird's beak regions are created around the periphery of the isolation structure. Consequently, IC devices that use (FOX) isolation structures are less amenable to high-density packing.
Shallow trench isolation is another method for isolating semiconductor devices. Shallow trench isolation entails the following procedures. First an anisotropic etching operation is conducted to form a trench in the semiconductor substrate. The trench is subsequently filled with silicon oxide. Since shallow trench isolation can prevent bird's beak encroachment, associated with the LOCOS method, it is an ideal method for forming deep sub-micron devices.
FIGS. 1A through 1C are schematic cross-sectional views showing the progression of steps for producing a conventional shallow trench isolation structure.
As shown in FIG. 1, a pad oxide layer 102 and a silicon nitride layer 104 are formed over the substrate 100. Using the silicon nitride layer 104 as an etching mask, a trench 106 is etched in the substrate 100. A linear oxide layer 108 is formed on the surface of the exposed portion of the substrate 100. A silicon oxide layer 110 is formed above the substrate 100, covering the silicon nitride layer 104 and filling the trench 106.
As shown in FIG. 1B, the silicon nitride layer 104 is used as a polishing stop layer to carry out a chemical mechanical polishing operation to remove excess silicon oxide layer and leave the silicon oxide layer 110 within the trench 106.
As shown in FIG. 1C, the silicon nitride layer 104 is removed. Through the application of hydrofluoric acid the pad oxide layer 102 is subsequently removed, leaving the isolation region formed by the silicon oxide layer 100 in the trench 106.
The size of devices and shallow trench isolation structures must be reduced, in order to enable higher levels of integration among high-density integrated circuits. In order to assure the effective isolation of devices, a predetermined width for shallow trench isolation structures must be established. Raising the concentration leads to a reduction in the surface area of the trench. A reduction in surface area of the trench increases the aspect ratio of the trench and, as a consequence, makes filling the trench more difficult. Specifically, if isolation material is not applied properly, then voids will formed within the shallow trench isolation structure.